1. Field of the Invention
The present invention relates to semiconductor packaging, and more particularly, the present invention relates to multichip module packaging.
2. The Background Art
The term "multichip module" is commonly used to refer to an electronic component having multiple integrated circuit dies that, when electronically combined, function as a system- or board-level unit. As seen in FIG. 1, the creation of the module usually includes receiving 10 each of the integrated circuit die, such as die 12 and die 14, in bare die form and attaching 16 each die to a suitable substrate 18. After attachment, the input/output (I/O) pads of each die are coupled electrically 20 to the I/O pads of substrate 18 either through a wire bonding process or flip-chip process. (The flip-chip process is not shown). An encapsulation step 22 is then preformed, where the integrated circuit dies 12 and 14, bonding wires 24 (if applicable), and substrate 18 are encapsulated by a protective material 26, such as epoxy. Encapsulation protects the bare dies and provides a robust and compact package, or multichip module 28, having all of the features that are offered by the combined integrated circuit dies.
At reference number 32, pin-out 30 is formed on substrate 18. Pin-out 30 is typically, but not always, formed opposite to the surface facing the attached integrated circuit die, and is for coupling electrically multichip module 28 to another substrate, such as a printed circuit board (not shown). Pin out 30 may be any high-density area connection (e.g., ball grid array, pin grid array or the like) or package configuration (e.g., dual in-line package (DIP), small out-line package (SOP), thin small out-line package (TSOP), small out-line J-lead (SOJ), quad flat pack (QFP), or the like). Multichip module 28 is then tested and burned-in to ensure proper operation (not shown).
FIG. 1 depicts the attachment and packaging of integrated circuit die onto a single substrate (shown in cross-section). Those of ordinary skill in the art will readily recognize that the substrate is typically part of a group of attached substrates (hereinafter referred to as a "substrate strip"). Hence, each of the substrates must be detached from the substrate strip after the formation of their corresponding multichip module but before testing and burn-in of each module. The entire substrate strip is not shown in FIG. 1 to avoid overcomplicating the disclosure.
Multichip module packaging technology has the advantage of shortening circuit design time because the designer is not constrained to design the entire target circuit or fabricate the entire target circuit on a single silicon die. Instead, the designer can obtain all or some of the integrated circuits from semiconductor vendors that produce the integrated circuits required in bare die form. For example, a graphics designer seeking to directly couple RAM memory functions with a graphics accelerator may obtain a DRAM integrated circuit die from a DRAM vendor. The graphics designer may then combine the DRAM integrated circuit die with the designer's graphics integrated circuit die by packaging the die circuits in a multichip module. Thus, a designer can rapidly construct a target circuit by obtaining some integrated circuit portions required in the target circuit from available vendors in bare die form.
However, multichip module technology is relatively expensive because module yield is dependent on the yield of each of the integrated circuit dies combined in each multichip module. Since each integrated circuit die used is packaged with other dies before system testing, any one die failing after packaging results in a defective multichip module regardless of whether the remaining dies in the module are not defective. The susceptibility of die failure after packaging due to use (such as when burned-in and/or tested for a period of time) is commonly known as die infant mortality. Die infant mortality increases packaging costs because the remaining integrated circuit dies in the module have already been encapsulated with the defective die and thus, cannot be re-used. Consequently, all it takes is one defective integrated circuit die in a multichip module to render the entire multichip module defective.
There have been prior attempts in identifying before packaging non-defective integrated circuit bare die, i.e., integrated circuit die that has the same level of quality as a die that as been packaged, tested, and burned-in. Such a non-defective integrated circuit in bare die form is commonly referred to as "known good die". One solution includes testing each integrated circuit in bare die form by placing the die in a suitable carrier or temporary package and then testing the circuit against a set of specified requirements. This solution is expensive because it includes using a temporary package or carrier, and inserting and removing the die from the temporary package or carrier.
In another approach, each integrated circuit die in bare die form is placed in a specialized and miniature test socket, tested, and burned-in before placement of each die onto the substrate. This requires strict tolerances because the I/O pads on the die must be aligned with the test carrier bare die sockets, which are used during die testing. In addition, this solution suffers from temperature and frequency limitations due to parasitic capacitance, cross talk, and cost.
Accordingly, there exists a need for an improved method of packaging integrated circuit dies into a multichip module.